GATE2025_CS1_Q11

Suppose a program is running on a non-pipelined single processor computer system. The computer is connected to an external device that can interrupt the processor asynchronously. The processor needs to execute the interrupt service routine (ISR) to serve this interrupt. The following steps (not necessarily in order) are taken by the processor when the interrupt arrives:

1. The processor saves the content of the program counter.
2. The program counter is loaded with the start address of the ISR.
3. The processor finishes the present instruction.

Which ONE of the following is the CORRECT sequence of steps?

✅ Final Answer:

The correct answer is option (A) (iii), (i), (ii).

🔹 Short Answer:

When an interrupt occurs, the processor first completes the currently executing instruction to ensure atomicity. Then, it saves the Program Counter (PC) so it knows where to resume later. Finally, it loads the address of the Interrupt Service Routine (ISR) into the PC to begin handling the interrupt. This corresponds to the sequence: Finish Instruction (iii) → Save PC (i) → Load ISR Address (ii).

🔸 Long Answer:

Understanding the sequence of operations during an interrupt is a fundamental concept in computer architecture. An interrupt forces a context switch from the current program to a special handler routine. This switch must be handled in a precise order to ensure the system remains stable and the original program can be resumed without error.

The Interrupt Handling Sequence

1. (iii) The processor finishes the present instruction.
   This is the first and most critical step. A processor's instruction cycle (Fetch, Decode, Execute) is an atomic unit. Interrupts are typically checked for and handled *between* instructions, not in the middle of one. This guarantees that the processor is in a consistent and predictable state before it switches context to the ISR. If an interrupt were handled mid-instruction, registers might hold intermediate values, leading to data corruption upon resumption.
2. (i) The processor saves the content of the program counter.
   After completing the current instruction, the Program Counter (PC) automatically holds the memory address of the *next* instruction that the original program was supposed to execute. To be able to return to the correct place after the interrupt is handled, this address must be saved. It is typically pushed onto a dedicated memory area called the system stack. Along with the PC, other registers (the processor status word, general-purpose registers) are also often saved.
3. (ii) The program counter is loaded with the start address of the ISR.
   With the return address safely stored, the processor must now branch to the interrupt handler. It does this by loading the start address of the appropriate ISR into the Program Counter. This action effectively hijacks the normal flow of execution and begins the execution of the ISR code. The system often uses an Interrupt Vector Table (IVT) to look up the correct ISR address based on the type of interrupt.

Conclusion

The logical and necessary order is to first reach a stable state (finish instruction), then save the context for later resumption (save PC), and finally transfer control to the handler (load ISR address). Any other sequence would either corrupt the program state or lose the return address.

Therefore, the correct sequence is (iii) → (i) → (ii).

Bibliography:
- Stallings, W. (2016). Computer Organization and Architecture: Designing for Performance. Pearson. (Chapter 4: Control Unit Operation).
- Patterson, D. A., & Hennessy, J. L. (2017). Computer Organization and Design: The Hardware/Software Interface. Morgan Kaufmann.

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